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complete quad, 14-bit, high accuracy, serial input, bipolar voltage output dac ad5744r rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features complete quad, 14-bit digital-to-analog converter (dac) programmable output range: 10 v, 10.2564 v, or 10.5263 v 1 lsb maximum inl error, 1 lsb maximum dnl error low noise: 60 nv/hz settling time: 10 s maximum integrated reference buffers internal reference: 10 ppm/c maximum on-chip die temperature sensor output control during power-up/brownout programmable short-circuit protection simultaneous updating via ldac asynchronous clr to zero code digital offset and gain adjust logic output control pins dsp-/microcontroller-compatible serial interface temperature range: ?40c to +85c i cmos process technology applications industrial automation open-loop/closed-loop servo control process control data acquisition systems automatic test equipment automotive test and measurement high accuracy instrumentation general description the ad5744r is a quad, 14-bit, serial input, bipolar voltage output dac that operates from supply voltages of 11.4 v to 16.5 v. nominal full-scale output range is 10 v. the ad5744r provides integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry. the part also features a digital i/o port, programmed via the serial interface, and an analog temperature sensor. the part incorporates digital offset and gain adjust registers per channel. the ad5744r is a high performance converter that provides guaranteed monotonicity, integral nonlinearity (inl) of 1 lsb, low noise, and 10 s settling time. the ad5744r includes an on- chip 5 v reference with a reference temperature coefficient of 10 ppm/c maximum. during power-up when the supply voltages are changing, voutx is clamped to 0 v via a low impedance path. the ad5744r is based on the i cmos? technology platform, which is designed for analog systems designers within industrial/instru- mentation equipment oems who need high performance ics at higher voltage levels. i cmos enables the development of analog ics capable of 30 v and operation at 15 v supplies, while allowing reductions in power consumption and package size, coupled with increased ac and dc performance. the ad5744r uses a serial interface that operates at clock rates of up to 30 mhz and is compatible with dsp and microcontroller interface standards. double buffering allows the simultaneous updating of all dacs. the input coding is programmable to either twos complement or offset binary formats. the asynchronous clear function clears all dac registers to either bipolar zero or zero scale, depending on the coding used. the ad5744r is ideal for both closed-loop servo control and open-loop control applications. the ad5744r is available in a 32-lead tqfp and offers guaranteed specifications over the ?40c to +85c industrial temperature range (see figure 1 for the functional block diagram).
ad5744r rev. a | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? functional block diagram .............................................................. 3 ? specifications ..................................................................................... 4 ? ac performance characteristics ................................................ 6 ? timing characteristics ................................................................ 7 ? absolute maximum ratings .......................................................... 10 ? thermal resistance .................................................................... 10 ? esd caution ................................................................................ 10 ? pin configuration and function descriptions ........................... 11 ? typical performance characteristics ........................................... 13 ? terminology .................................................................................... 19 ? theory of operation ...................................................................... 21 ? dac architecture ....................................................................... 21 ? reference buffers ........................................................................ 21 ? serial interface ............................................................................ 21 ? simultaneous updating via ldac ........................................... 23 ? transfer function ....................................................................... 23 ? asynchronous clear ( clr ) ....................................................... 23 ? registers ........................................................................................... 24 ? function register ....................................................................... 24 ? data register ............................................................................... 25 ? coarse gain register ................................................................. 25 ? fine gain register ...................................................................... 25 ? design features ............................................................................... 26 ? analog output control ............................................................. 26 ? programmable short-circuit protection ................................ 26 ? digital i/o port ........................................................................... 26 ? die temperature sensor ............................................................ 26 ? local ground offset adjust ...................................................... 26 ? applications information .............................................................. 27 ? typical operating circuit ......................................................... 27 ? layout guidelines ........................................................................... 29 ? galvanically isolated interface ................................................. 29 ? microprocessor interfacing ....................................................... 29 ? outline dimensions ....................................................................... 30 ? ordering guide .......................................................................... 30 ? revision history 12/08rev. 0 to rev. a changes to figure 1 .......................................................................... 3 10/08revision 0: initial version
ad5744r rev. a | page 3 of 32 functional block diagram input reg c gain reg c dac reg c 14 dac c input reg d gain reg d dac reg d 14 dac d g1 g2 input reg b gain reg b dac reg b 14 dac b input reg a gain reg a dac 5v reference reg a 14 14 dac a ldac refcd rstin rstout refab refgnd agndd voutd agndc voutc agndb voutb agnda vouta iscc reference buffers sdin sclk sync sdo d0 d1 bin/2scomp clr pgnd dv cc dgnd g1 g2 g1 g2 g1 g2 av dd av ss av dd input shift register and control logic voltage monitor and control reference buffers temp sensor temp av ss refout ad5744r 06065-001 figure 1.
ad5744r rev. a | page 4 of 32 specifications av dd = 11.4 v to 16.5 v, av ss = ?11.4 v to ?16.5 v, agnd = dgnd = refgnd = pgnd = 0 v; refab = refcd = 5 v external; dv cc = 2.7 v to 5.25 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 1. parameter min typ max unit test conditions/comments 1 accuracy outputs unloaded resolution 14 bits relative accuracy (inl) ?1 +1 lsb differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic bipolar zero error ?2 +2 mv 25c; error at other temperatures obtained using bipolar zero tempco ?3 +3 mv bipolar zero tempco 2 ?2 +2 ppm fsr/c zero-scale error ?2 +2 mv 25c; error at other temperatures obtained using zero-scale tempco ?2.5 +2.5 mv zero-scale tempco 2 ?2 +2 ppm fsr/c gain error ?0.02 +0.02 % fsr gain tempco 2 ?2 +2 ppm fsr/c dc crosstalk 2 0.125 lsb reference input/output reference input 2 reference input voltage 5 v 1% for specified performance dc input impedance 1 m typically 100 m input current ?10 +10 a typically 30 na reference range 1 7 v reference output output voltage 4.995 5 5.005 v 25c, av dd /av ss = 13.5 v reference tempco 2 ?10 1.7 +10 ppm/c r load 2 1 m power supply sensitivity 1 300 v/v output noise 2 18 v p-p 0.1 hz to 10 hz noise spectral density 2 75 nv/hz 10 khz output voltage drift vs. time 2 40 ppm/500 hr 50 ppm/1000 hr thermal hysteresis 1 70 ppm first temperature cycle 30 ppm subsequent temperature cycles output characteristics 2 output voltage range 3 ?10.5263 +10.5263 v av dd /av ss = 11.4 v, refin = 5 v ?14.7368 +14.7368 v av dd /av ss = 16.5 v, refin = 7 v output voltage drift vs. time 13 ppm fsr/500 hr 15 ppm fsr/1000 hr short-circuit current 10 ma r iscc = 6 k, see figure 31 load current ?1 +1 ma for specified performance capacitive load stability r load = 200 pf r load = 10 k 1000 pf dc output impedance 0.3
ad5744r rev. a | page 5 of 32 parameter min typ max unit test conditions/comments 1 digital inputs 2 dv cc = 2.7 v to 5.25 v input high voltage, v ih 2.4 v input low voltage, v il 0.8 v input current ?1.2 +1.2 a per pin pin capacitance 10 pf per pin digital outputs (d0, d1, sdo) 2 output low voltage 0.4 v dv cc = 5 v 5%, sinking 200 a output high voltage dv cc ? 1 v dv cc = 5 v 5%, sourcing 200 a output low voltage 0.4 v dv cc = 2.7 v to 3.6 v, sinking 200 a output high voltage dv cc ? 0.5 v dv cc = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current ?1 +1 a sdo only high impedance output capacitance 5 pf sdo only die temperature sensor 2 output voltage at 25c 1.47 v die temperature output voltage scale factor 5 mv/c output voltage range 1.175 1.9 v ?40c to +105c output load current 200 a current source only power-on time 80 ms power requirements av dd +11.4 +16.5 v av ss ?11.4 ?16.5 dv cc 2.7 5.25 v power supply sensitivity 2 ?v out /?v dd ?85 db ai dd 3.55 ma/channel outputs unloaded ai ss 2.8 ma/channel outputs unloaded di cc 1.2 ma v ih = dv cc , v il = dgnd, 750 a typ power dissipation 275 mw 12 v operation output unloaded 1 temperature range: ?40c to + 85c; typical at +25c. device functionality is guaranteed to 105c with degraded performance. 2 guaranteed by design and characterization; not production tested. 3 output amplifier headroom requirement is 1.4 v minimum.
ad5744r rev. a | page 6 of 32 ac performance characteristics av dd = 11.4 v to 16.5 v, av ss = ?11.4 v to ?16.5 v, agnd = dgnd = refgnd = pgnd = 0 v; refab = refcd = 5 v external; dv cc = 2.7 v to 5.25 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 2. parameter min typ max unit test conditions/comments dynamic performance 1 output voltage settling time 8 s full-scale step to 1 lsb 10 s 2 s 512 lsb step settling slew rate 5 v/s digital-to-analog glitch energy 8 nv-sec glitch impulse peak amplitude 25 mv channel-to-channel isolation 80 db dac-to-dac crosstalk 8 nv-sec digital crosstalk 2 nv-sec digital feedthrough 2 nv-sec effect of input bus activity on dac outputs output noise (0.1 hz to 10 hz) 0.025 lsb p-p output noise (0.1 hz to 100 khz) 45 v rms 1/f corner frequency 1 khz output noise spectral density 60 nv/hz measured at 10 khz complete system output noise spectral density 2 80 nv/hz measured at 10 khz 1 guaranteed by design and characterization; not production tested. 2 includes noise contributions from integrated reference buffers, 14-bit dac, and output amplifier.
ad5744r rev. a | page 7 of 32 timing characteristics av dd = 11.4 v to 16.5 v, av ss = ?11.4 v to ?16.5 v, agnd = dgnd = refgnd = pgnd = 0 v; refab = refcd = 5 v external; dv cc = 2.7 v to 5.25 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 4 13 ns min 24 th sclk falling edge to sync rising edge t 6 40 ns min minimum sync high time t 7 2 ns min data setup time t 8 5 ns min data hold time t 9 1.7 s min sync rising edge to ldac falling edge (all dacs updated) 480 ns min sync rising edge to ldac falling edge (single dac updated) t 10 10 ns min ldac pulse width low t 11 500 ns max ldac falling edge to dac output response time t 12 10 s max dac output settling time t 13 10 ns min clr pulse width low t 14 2 s max clr pulse activation time t 15 5 , 6 25 ns max sclk rising edge to sdo valid t 16 13 ns min sync rising edge to sclk falling edge t 17 2 s max sync rising edge to dac output response time (ldac = 0) t 18 170 ns min ldac falling edge to sync rising edge 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, and figure 4. 4 standalone mode only. 5 measured with the load circuit of figure 5. 6 daisy-chain mode only.
ad5744r rev. a | page 8 of 32 timing diagrams db23 sclk sync sdin ldac ldac = 0 clr 12 24 db0 t 1 voutx voutx voutx t 4 t 6 t 3 t 2 t 5 t 8 t 7 t 10 t 9 t 10 t 11 t 12 t 12 t 17 t 18 t 13 t 14 06065-002 figure 2. serial interface timing diagram ldac sdo sdin sync sclk 24 48 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n?1 input word for dac n db0 t 1 t 2 t 3 t 4 t 6 t 7 t 8 t 15 t 16 t 5 t 10 t 9 06065-003 figure 3. daisy-chain timing diagram
ad5744r rev. a | page 9 of 32 sdo sdin s yn c sclk 24 48 db23 db0 db23 db0 db23 undefined nop condition db0 input word specifies register to be read selected register data clocked out 06065-004 figure 4. readback timing diagram 200a i ol 200a i oh v oh (min) or v ol (max) to output pin c l 50pf 06065-005 figure 5. load circuit for sdo timing diagram
ad5744r rev. a | page 10 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. parameter rating av dd to agnd, dgnd ?0.3 v to +17 v av ss to agnd, dgnd +0.3 v to ?17 v dv cc to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to (dv cc + 0.3 v) or +7 v, whichever is less digital outputs to dgnd ?0.3 v to dv cc + 0.3 v refin to agnd, pgnd ?0.3 v to av dd + 0.3 v refout to agnd av ss to av dd temp av ss to av dd voutx to agnd av ss to av dd agnd to dgnd ?0.3 v to +0.3 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 150c lead temperature (soldering) jedec industry standard j-std-020 thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance package type ja jc unit 32-lead tqfp 65 12 c/w esd caution
ad5744r rev. a | page 11 of 32 pin configuration and fu nction descriptions sync sclk sdin sdo clr ldac d1 d0 agnda vouta voutb agndb agndc voutc voutd agndd rstout rstin dgnd dv cc av dd pgnd iscc av ss bin/2scomp av dd av ss temp refgnd refout refcd refab 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 pin 1 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad5744r top view (not to scale) 0 6065-006 figure 6. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 sync active low input. this is the frame synchronization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. 2 sclk serial clock input. data is clocked in to the shift register on the falling edge of sclk. this operates at clock speeds of up to 30 mhz. 3 sdin serial data input. data must be valid on the falling edge of sclk. 4 sdo serial data output. this pin is us ed to clock data from the serial register in daisy-chain or readback mode. 5 clr negative edge triggered input. 1 asserting this pin sets the dac registers to 0x0000. 6 ldac load dac. this logic input is used to update the dac registers and, consequently, the analog outputs. when tied permanently low, the addressed dac regi ster is updated on the rising edge of sync . if ldac is held high during the write cycle, the dac input register is updated, but the output update is held off until the falling edge of ldac . in this mode, all analog outputs can be up dated simultaneously on the falling edge of ldac . the ldac pin must not be left unconnected. 7, 8 d0, d1 digital i/o port. d0 and d1 form a digital i/o port. the us er can set up these pins as inputs or outputs that are configurable and readable over the serial interface. when configured as inputs, thes e pins have weak internal pull-ups to dv cc . when programmed as outputs, d0 and d1 are referenced by dv cc and dgnd. 9 rstout reset logic output. this is the output from the on-chip vo ltage monitor used in the reset circuit. if desired, it can be used to control other system components. 10 rstin reset logic input. this input allows exte rnal access to the internal reset logic. applying a logic 0 to this input clamps the dac outputs to 0 v. in normal operation, rstin should be tied to logic 1. register values remain unchanged. 11 dgnd digital ground pin. 12 dv cc digital supply pin. voltage ranges from 2.7 v to 5.25 v. 13, 31 av dd positive analog supply pins. voltage ranges from 11.4 v to 16.5 v. 14 pgnd ground reference point for analog circuitry. 15, 30 av ss negative analog supply pins. voltage ranges from C11.4 v to C16.5 v. 16 iscc this pin is used in association with an optional external resistor to agnd to program the short-circuit current of the output amplifiers. refer to the design features section for more information. 17 agndd ground reference pin for dac d output amplifier. 18 voutd analog output voltage of dac d. buffered output with a nominal full-scale output range of 10 v. the output amplifier is capable of directly driving a 10 k, 200 pf load. 19 voutc analog output voltage of dac c. buffered output with a nominal full-scale output range of 10 v. the output amplifier is capable of directly driving a 10 k, 200 pf load. 20 agndc ground reference pin for dac c output amplifier. 21 agndb ground reference pin for dac b output amplifier. 22 voutb analog output voltage of dac b. buffered output with a nominal full-scale output range of 10 v. the output amplifier is capable of directly driving a 10 k, 200 pf load.
ad5744r rev. a | page 12 of 32 pin no. mnemonic description 23 vouta analog output voltage of dac a. buffered output with a nominal full-scale output range of 10 v. the output amplifier is capable of directly driving a 10 k, 200 pf load. 24 agnda ground reference pin for dac a output amplifier. 25 refab external reference voltage input for channel a and channel b. the reference input range is 1 v to 7 v, and it programs the full-scale output voltage. refin = 5 v for specified performance. 26 refcd external reference voltage input for channel c and channel d. the reference input range is 1 v to 7 v, and it programs the full-scale output voltage. refin = 5 v for specified performance. 27 refout reference output. this is the reference output from the inte rnal voltage reference. the internal reference is 5 v 3 mv at 25c, with a reference temperature coefficient of 10 ppm/c. 28 refgnd reference ground return for the reference generator and buffers. 29 temp this pin provides an output voltage proportional to temp erature. the output voltage is 1.47 v typical at 25c die temperature; variation with temperature is 5 mv/c. 32 bin/ 2scomp this pin determines the dac coding. this pin should be hardwired to either dv cc or dgnd. when hardwired to dv cc , input coding is offset binary (see table 7 ). when hardwired to dgnd, input coding is twos complement (see table 8 ). 1 internal pull-up device on this logic input. therefore, it can be left floating; and it defaults to a logic high condition.
ad5744r rev. a | page 13 of 32 typical performance characteristics 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 inl error (lsb) dac code t a = 25c v dd /v ss = 15v refin = 5v 06065-009 figure 7. integral nonlinearity error vs. dac code, v dd /v ss = 15 v 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 inl error (lsb) dac code t a = 25c v dd /v ss = 12v refin = 5v 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 06065-010 figure 8. integral nonlinearity error vs. dac code, v dd /v ss = 12 v 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 dnl error (lsb) dac code t a = 25c v dd /v ss = 15v refin = 5v 06065-013 figure 9. differential nonlinearity error vs. dac code, v dd /v ss = 15 v 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 16,000 14,000 12,000 10,000 8000 6000 4000 2000 dnl error (lsb) dac code t a = 25c v dd /v ss = 12v refin = 5v 06065-014 figure 10. differential nonlinearity error vs. dac code, v dd /v ss = 12 v 0.12 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 100 ?200 20406080 inl error (lsb) temperature (c) 06065-015 v dd /v ss = 15v refin = 5v figure 11. integral nonlinearity error vs. temperature, v dd /v ss = 15 v 0.12 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 ?40 100 ?20 0 20 40 60 80 inl error (lsb) temperature (c) 06065-016 v dd /v ss = 12v refin = 5v figure 12. integral nonlinearity error vs. temperature, v dd /v ss = 12 v
ad5744r rev. a | page 14 of 32 0.04 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 ?40 100 ?20 0 20 40 60 80 dnl error (lsb) temperature (c) 06065-019 v dd /v ss = 15v refin = 5v figure 13. differential nonlinearity error vs. temperature, v dd /v ss = 15 v 0.04 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 ?40 100 ?20 0 20 40 60 80 dnl error (lsb) temperature (c) 06065-020 v dd /v ss = 12v refin = 5v figure 14. differential nonlinearity error vs. temperature, v dd /v ss = 12 v 0.12 ?0.04 ?0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 11.4 16.4 15.4 14.4 13.4 12.4 inl error (lsb) supply voltage (v) 06065-023 t a = 25c refin = 5v figure 15. integral nonlinearity error vs. supply voltage 0.15 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 11.4 16.4 15.4 14.4 13.4 12.4 dnl error (lsb) supply voltage (v) t a = 25c refin = 5v 06065-025 figure 16. differential nonlinearity error vs. supply voltage 0.20 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 17 56 4 3 2 inl error (lsb) reference voltage (v) 06065-027 t a = 25c v dd /v ss = 15v figure 17. integral nonlinearity error vs. reference voltage v dd /v ss = 15 v 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 17 56 4 3 2 dnl error (lsb) reference voltage (v) 06065-031 t a = 25c v dd /v ss = 16.5v figure 18. differential nonlinearity error vs. reference voltage v dd /v ss = 16.5 v
ad5744r rev. a | page 15 of 32 0.6 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 17 56 4 3 2 tue (mv) reference voltage (v) t a = 25c 06065-035 figure 19. total unadjusted error vs. reference voltage, v dd /v ss = 16.5 v 14 13 12 11 10 9 8 11.4 16.4 15.4 14.4 13.4 12.4 current (ma) v dd /v ss (v) t a = 25c refin = 5v |i ss | |i dd | 06065-037 figure 20. i dd /i ss vs. v dd /v ss 0.25 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 ?40 100 80 60 40 20 0 ?20 zero-scale error (mv) temperature (c) refin = 5v v dd /v ss = 15v v dd /v ss = 12v 06065-038 figure 21. zero-scale error vs. temperature 0.8 0.6 0.4 ?0.4 ?0.2 0 0.2 ?40 100 80 60 40 20 0 ?20 bipolar zero error (mv) temperature (c) refin = 5v v dd /v ss = 15v v dd /v ss = 12v 06065-039 figure 22. bipolar zero error vs. temperature 1.4 0.6 0.8 1.0 1.2 0.4 ?0.2 0 0.2 ?40 100 80 60 40 20 0 ?20 gain error (mv) temperature (c) refin = 5v v dd /v ss = 15v v dd /v ss = 12v 06065-040 figure 23. gain error vs. temperature 0.0014 0.0013 0.0012 0.0011 0.0010 0.0009 0.0008 0.0007 0.0006 05 4.54.03.53.02.5 2.01.51.00.5 di cc (ma) v logic (v) . 0 t a = 25c 5v 3v 06065-041 figure 24. di cc vs. logic input voltage
ad5744r rev. a | page 16 of 32 7000 3000 4000 5000 6000 2000 ?1000 0 1000 ?10 10 5 0 ?5 output voltage delta (v) source/sink current (ma) t a = 25c refin = 5v v dd /v ss = 15v v dd /v ss = 12v 06065-042 figure 25. source and sink capability of output amplifier with positive full scale loaded 10,000 7000 8000 9000 3000 4000 5000 6000 2000 ?1000 0 1000 ?12 8 3 ?2 ?7 output voltage delta (v) source/sink current (ma) t a = 25c refin = 5v 06065-043 v dd /v ss = 15v v dd /v ss = 12v figure 26. source and sink capability of output amplifier with negative full scale loaded ch1 3.00v m1.00s ch1 ?120mv 1 v dd /v ss = 15v t a = 25c refin = 5v 1s/div 06065-044 figure 27. full-scale settling time ? 4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 ?20 ?22 ?24 ?26 ?2.0?1.5?1.0?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v out (mv) time (s) v dd /v ss = 12v, refin = 5v, t a = 25c, 0x8000 to 0x7fff, 500ns/div 06065-047 figure 28. major code transition glitch energy, v dd /v ss = 12 v ch4 50.0v m1.00s ch4 26v 4 v dd /v ss = 15v midscale loaded refin = 0v 50v/div 06065-048 figure 29. peak-to-peak noise (100 khz bandwidth) ch1 10.0v b w ch3 10.0mv b w t 29.60% ch2 10.0v m100s a ch1 7.80mv 1 2 3 v dd /v ss = 12v, refin = 5v, t a = 25c, ramp time = 100s, load = 200pf||10k ? t 06065-055 figure 30. voutx vs. v dd /v ss on power-up
ad5744r rev. a | page 17 of 32 10 9 8 7 6 5 4 3 2 1 0 0 120 100 80 60 40 20 short-circuit current (ma) r iscc (k ? ) v dd /v ss = 15v t a = 25c refin = 5v 06065-050 figure 31. short-circuit current vs. r iscc ch1 10.0v b w ch3 5.00v b w t 29.60% ch2 10.0v m400s a ch1 7.80mv 1 2 3 v dd /v ss = 12v t a = 25c t 06065-054 figure 32. refout turn-on transient ch1 50.0v m1.00s a ch1 15v 1 v dd /v ss = 12v t a = 25c, 10f capacitor on refout 50v/div 06065-052 figure 33. refout output noise 100 khz bandwidth m1.00s a ch1 18mv 1 v dd /v ss = 12v t a = 25c 5v/div 06065-053 figure 34. refout output noise 0.1 hz to 10 hz reference output voltage (v) load current (a) 06065-032 0 1 2 3 4 5 6 0 20 40 60 80 100 120 140 160 180 200 t a = 25c v dd /v ss = 15v figure 35. refout load regulation 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 ?40 ?20 0 20 40 60 80 100 temperature output voltage (v) temperature (c) 06065-033 t a = 25c v dd /v ss = 15v figure 36. temperature output voltage vs. temperature
ad5744r rev. a | page 18 of 32 06065-072 temperature drift (ppm/c) population (%) 0 5 10 15 20 25 30 35 40 0.51.52.53.54.55.56.57.58.59.5 max: 10ppm/c typ: 1.7ppm/c 06065-070 temperature (c) reference output voltage (v) 4.997 4.998 4.999 5.000 5.001 5.002 5.003 ?40 ?20 0 20 40 60 80 100 20 devices shown figure 37. reference output voltage vs. temperature figure 38. reference output temperature drift (?40c to +85c)
ad5744r rev. a | page 19 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity (dnl) the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5744r is monotonic over its full operating temperature range. bipolar zero error the deviation of the analog output from the ideal half-scale output of 0 v when the dac register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement coding). figure 22 shows a plot of bipolar zero error vs. temperature. bipolar zero temperature coefficient the measure of the change in the bipolar zero error with a change in temperature. it is expressed as parts per million of full-scale range per degree celsius (ppm fsr/c). full-scale error the measure of the output error when full-scale code is loaded to the dac register. ideally, the output voltage should be 2 v refin ? 1 lsb. full-scale error is expressed as a percentage of full-scale range (% fsr). negative full-scale error/zero-scale error the error in the dac output voltage when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the dac register. ideally, the output voltage should be ?2 v refin . figure 21 shows a plot of zero-scale error vs. temperature. output voltage settling time the amount of time it takes for the output to settle to a specified level for a full-scale input change. slew rate a limitation in the rate of change of the output voltage. the output slewing speed of a voltage output dac is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in volts per microsecond (v/s). gain error a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range (% fsr). figure 23 shows a plot of gain error vs. temperature. tot a l un a dju s te d e r ror ( t u e ) a measure of the output error, considering all the various errors. figure 19 shows a plot of total unadjusted error vs. reference voltage. zero-scale error temperature coefficient a measure of the change in zero-scale error with a change in temperature. it is expressed as parts per million of full-scale range per degree celsius (ppm fsr/c). gain error temperature coefficient a measure of the change in gain error with changes in tempera- ture. it is expressed as parts per million of full-scale range per degree celsius (ppm fsr/c). digital-to-analog glitch energy the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nanovolt-seconds (nv-sec) and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000), as shown in figure 28 . digital feedthrough a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nanovolt-seconds (nv-sec) and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa. power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage. dc crosstalk the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full- scale output change on one dac while monitoring another dac, and is expressed in least significant bits (lsbs). dac-to-dac crosstalk the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (from all 0s to all 1s, and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in nanovolt-seconds (nv-sec). channel-to-channel isolation the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in decibels (db). reference temperature coefficient a measure of the change in the reference output voltage with a change in temperature. it is expressed in parts per million per degree celsius (ppm/c).
ad5744r rev. a | page 20 of 32 digital crosstalk a measure of the impulse injected into the analog output of one dac from the digital inputs of another dac but is measured when the dac output is not updated. it is specified in nanovolt- seconds (nv-sec) and measured with a full-scale code change on the data bus; that is, from all 0s to all 1s, and vice versa. thermal hysteresis the change of reference output voltage after the device is cycled through temperatures from ?40c to +85c and back to ?40c. this is a typical value from a sample of parts put through such a cycle.
ad5744r rev. a | page 21 of 32 theory of operation the ad5744r is a quad, 14-bit, serial input, bipolar voltage output dac that operates from supply voltages of 11.4 v to 16.5 v and has a buffered output voltage of up to 10.5263 v. data is written to the ad5744r in a 24-bit word format via a 3-wire serial interface. the ad5744r also offers an sdo pin that is available for daisy chaining or readback. the ad5744r incorporates a power- on reset circuit that ensures that the dac registers are loaded with 0x0000 at power-up. the ad5744r features a digital i/o port that can be programmed via the serial interface, an analog die temperature sensor, on-chip 10 ppm/c voltage reference, on-chip reference buffers, and per channel digital gain and offset registers. dac architecture the dac architecture of the ad5744r consists of a 14-bit current mode segmented r-2r dac. the simplified circuit diagram for the dac section is shown in figure 39 . 06065-060 2r e15 v ref 2r e14 e1 2r s11 rr r 2r s10 2r 12-bit, r-2r ladder 4 msbs decoded into 15 equal segments voutx 2r s0 2r agndx r/8 i out figure 39. dac ladder structure the four msbs of the 14-bit data-word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of the 15 matched resistors to either agndx or i out . the remaining 12 bits of the data-word drive switch s0 to switch s11 of the 12-bit r-2r ladder network. reference buffers the ad5744r can operate with either an external or an internal reference. the reference inputs (refab and refcd) have an input range of up to 7 v. this input voltage is then used to provide a buffered positive and negative reference for the dac cores. the positive reference is given by +v ref = 2 v refin the negative reference to the dac cores is given by ?v ref = ?2 v refin these positive and negative reference voltages (along with the gain register values) define the output ranges of the dacs. serial interface the ad5744r is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi, qspi?, microwire?, and dsp standards. input shift register the input shift register is 24 bits wide. data is loaded into the device, msb first, as a 24-bit word under the control of a serial clock input, sclk. the input register consists of a read/write bit, a reserved bit that must be set to 0, three register select bits, three dac address bits, and 16 data bits, as shown in table 9 . the timing diagram for this operation is shown in figure 2 . upon power-up, the dac registers are loaded with zero code (0x0000), and the outputs are clamped to 0 v via a low impedance path. the outputs can be updated with the zero code value by asserting either ldac or clr . the corresponding output voltage depends on the state of the bin/ 2scomp pin. if the bin/ 2scomp pin is tied to dgnd, the data coding is twos complement and the outputs update to 0 v. if the bin/ 2scomp pin is tied to dv cc , the data coding is offset binary and the outputs update to negative full scale. to have the outputs power-up with zero code loaded to the outputs, the clr pin should be held low during power-up. standalone operation the serial interface works with both a continuous and noncon- tinuous serial clock. a continuous sclk source can be used only if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. the first falling edge of sync starts the write cycle. exactly 24 falling clock edges must be applied to sclk before sync is brought high again. if sync is brought high before the 24 th falling sclk edge, the data written is invalid. if more than 24 falling sclk edges are applied before sync is brought high, the input data is also invalid. the input register addressed is updated on the rising edge of sync . for another serial transfer to take place, sync must be brought low again. after the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register. when the data has been transferred into the chosen register of the addressed dac, all dac registers and outputs can be updated by taking ldac low.
ad5744r rev. a | page 22 of 32 68hc11* miso sync sdin sclk mosi sck pc7 pc6 ldac sdo sync sclk ldac sdo sync sclk ldac sdo sdin sdin *additional pins omitted for clarity. ad5744r* ad5744r* ad5744r* 06065-061 figure 40. daisy-chaining the ad5744r daisy-chain operation for systems that contain several devices, the sdo pin can be used to daisy-chain several devices together. this daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. the first falling edge of sync starts the write cycle. the sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the sdin input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24 n , where n is the total number of ad5744r devices in the chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the serial clock can be a continuous or a gated clock. a continuous sclk source can be used only if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. readback operation be fore a readback operation is initiated, the sdo pin must be enabled by writing to the function register and clearing the sdo disable bit; this bit is cleared by default. readback mode is invoked by setting the r/ w bit to 1 in the serial input register write. with r/ w set to 1, bit a2 to bit a0, in association with bit reg2, to bit reg0, select the register to be read. the remaining data bits in the write sequence are dont care. during the next spi write, the data appearing on the sdo output contain the data from the previously addressed register. for a read of a single register, the nop command can be used in clocking out the data from the selected register on sdo. the readback diagram in shows the readback sequence. for example, to read back the fine gain register of channel a, implement the following sequence: figure 4 1. write 0xa0xxxx to the input register. this write configures the ad5744r for read mode with the fine gain register of channel a selected. note that all the data bits, db15 to db0, are dont care. 2. follow with a second write: an nop condition, 0x00xxxx. during this write, the data from the fine gain register is clocked out on the sdo line; that is, data clocked out contains the data from the fine gain register in bit db5 to bit db0.
ad5744r rev. a | page 23 of 32 simultaneous updating via ldac transfer function table 7 and table 8 show the ideal input code to output voltage relationship for offset binary data coding and twos complement data coding, respectively. depending on the status of both sync and ldac , and after data has been transferred into the input register of the dacs, there are two ways to update the dac registers and dac outputs. the output voltage expression for the ad5744r is given by individual dac updating in individual dac updating mode, ldac is held low while data is being clocked into the input shift register. the addressed dac output is updated on the rising edge of sync . v out = ?2 v refin + 4 v refin ? ? ? ? ? ? 384,16 d where: d is the decimal equivalent of the code loaded to the dac. v refin is the reference voltage applied at the refab and refcd pins. simultaneous updating of all dacs in simultaneous updating of all dacs mode, ldac is held high while data is being clocked into the input shift register. all dac outputs are updated by taking ldac low any time after sync has been taken high. the update then occurs on the falling edge of ldac . asynchronous clear ( clr ) clr is a negative edge triggered clear that allows the outputs to be cleared to either 0 v (twos complement coding) or negative full scale (offset binary coding). it is necessary to maintain clr low for a minimum amount of time for the operation to complete (see ). when the figure 2 clr signal is returned high, the output remains at the cleared value until a new value is programmed. if clr is at 0 v at power-on, all dac outputs are updated with the clear value. a clear can also be initiated through software by writing the command of 0x04xxxx to the ad 5744r. see figure 41 for a simplified block diagram of the dac load circuitry. voutx dac register interface logic output i/v amplifier ldac sdo sdin 14-bit dac refab, refcd sync input register sclk 06065-062 figure 41. simplified serial interface of input loading circuitry for one dac channel table 7. ideal output voltage to input code relationship?offset binary data coding digital input analog output msb lsb v out 11 1111 1111 1111 +2 v ref (8191/8192) 10 0000 0000 0001 +2 v ref (1/8192) 10 0000 0000 0000 0 v 01 1111 1111 1111 ?2 v ref (1/8192) 00 0000 0000 0000 ?2 v ref (8191/8192) table 8. ideal output voltage to input code relationshiptwos complement data coding digital input analog output msb lsb v out 01 1111 1111 1111 +2 v ref (8191/8192) 00 0000 0000 0001 +2 v ref (1/8192) 00 0000 0000 0000 0 v 11 1111 1111 1111 ?2 v ref (1/8192) 10 0000 0000 0000 ?2 v ref (8191/8192)
ad5744r rev. a | page 24 of 32 registers table 9. input shift register format msb lsb db23 db22 db21 db20 db19 db 18 db17 db16 db15 to db0 r/ w 0 reg2 reg1 reg0 a2 a1 a0 data table 10. input shift register bit function descriptions register bit description r/ w indicates a read from or a write to the addressed register reg2, reg1, reg0 used in association with the address bits, determines if a read or write operation is to the data register, offset register, gain register, or function register. reg2 reg1 reg0 function 0 0 0 function register 0 1 0 data register 0 1 1 coarse gain register 1 0 0 fine gain register a2, a1, a0 decodes the dac channels a2 a1 a0 channel address 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 0 0 all dacs data data bits function register the function register is addressed by setting the three reg bits to 000. the values written to the address bits and the data bi ts determine the function addressed. the functions available via the function register are outlined in table 11 and table 12 . table 11. function register options reg2 reg1 reg0 a2 a1 a0 db15 to db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 nop, data = dont care 0 0 0 0 0 1 dont care local ground offset adjust d1 direction d1 value d0 direction d0 value sdo disable 0 0 0 1 0 0 clear, data = dont care 0 0 0 1 0 1 load, data = dont care table 12. explanation of function register options option description nop no operation instruction used in readback operations. local ground offset adjust set by the user to enable the loca l ground offset ad just function. cleared by the user to disable the local grou nd offset adjust function (default). see the design features section for more information. d0, d1 direction set by the user to enable the d0 and d1 pins as outputs. cleared by the user to enable the d0 and d1 pins as inputs (default). see the design features section for more information. d0, d1 value i/o port status bits. logic values written to these location s determine the logic outputs on the d0 and d1 pins when configured as outputs. these bits indicate the status of the d0 and d1 pins when th e i/o port is active as an input. when enabled as inputs, these bits are do nt cares during a write operation. sdo disable set by the user to disable the sdo output. cleared by the user to enable the sdo output (default). clear addressing this function resets the dac outputs to 0 v in twos complement mode and negative full scale in binary mode. load addressing this function updates the dac registers and, consequently, the analog outputs.
ad5744r rev. a | page 25 of 32 data register the data register is addressed by setting the three reg bits to 010. the dac address bits select the dac channel with which the data transfer takes place (see table 1 0 ). the data bits are positioned in db15 to db2, as shown in table 13 . table 13. programming the data register reg2 reg1 reg0 a2 a1 a0 db15 to db2 db1 db0 0 1 0 dac address 14-bit dac data x x coarse gain register the coarse gain register is addressed by setting the three reg bits to 011. the dac address bits select the dac channel with wh ich the data transfer takes place (see table 10 ). the coarse gain register is a 2-bit register that allows the user to select the output range of each dac as shown in table 15 . table 14. programming the coarse gain register reg2 reg1 reg0 a2 a1 a0 db15 to db2 db1 db0 0 1 1 dac address dont care cg1 cg0 table 15. output range selection output range cg1 cg0 10 v (default) 0 0 10.2564 v 0 1 10.5263 v 1 0 fine gain register the fine gain register is addressed by setting the three reg bits to 100. the dac address bits select the dac channel with whic h the data transfer takes place (see table 1 0 ). the ad5744r fine gain register is a 6-bit register that allows the user to adjust the gain of each dac channel by ?8 lsbs to +7.75 lsbs in 0.25 lsb steps, as shown in table 16 and table 17 . the adjustment is made to both the positive full- scale points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. the fine gain register coding is twos complement. table 16. programming the fine gain register reg2 reg1 reg0 a2 a1 a0 db15 to db6 db5 db4 db3 db2 db1 db0 1 0 0 dac address dont care fg5 fg4 fg3 fg2 fg1 fg0 table 17. fine gain register options gain adjustment fg5 fg4 fg3 fg2 fg1 fg0 +7.75 lsbs 0 1 1 1 1 1 +7.5 lsbs 0 1 1 1 1 0 no adjustment (default) 0 0 0 0 0 0 ?7.75 lsbs 1 0 0 0 0 1 ?8 lsbs 1 0 0 0 0 0
ad5744r rev. a | page 26 of 32 design features analog output control in many industrial process control applications, it is vital that the output voltage be controlled during power-up and during brownout conditions. when the supply voltages are changing, the voutx pins are clamped to 0 v via a low impedance path. to prevent the output amp from being shorted to 0 v during this time, transmission gate g1 is also opened (see figure 42 ). g1 g2 rstout rstin vouta agnda voltage monitor and control 06065-063 figure 42. analog output control circuitry these conditions are maintained until the power supplies stabilize and a valid word is written to the dac register. g2 then opens, and g1 closes. both transmission gates are also externally controllable via the reset in ( rstin ) control input. for example, if rstin is driven from a battery supervisor chip, the rstin input is driven low to open g1 and close g2 on power-off or during a brownout. conversely, the on-chip voltage detector output ( rstout ) is also available to the user to control other parts of the system. the basic transmission gate functionality is shown in . figure 42 programmable short-circuit protection the short-circuit current (i sc ) of the output amplifiers can be programmed by inserting an external resistor between the iscc pin and the pgnd pin. the programmable range for the current is 500 a to 10 ma, corresponding to a resistor range of 120 k to 6 k . the resistor value is calculated as follows: r sc i 60 if the iscc pin is left unconnected, the short-circuit current limit defaults to 5 ma. it should be noted that limiting the short- circuit current to a small value can affect the slew rate of the output when driving into a capacitive load. therefore, the value of the short-circuit current that is programmed should take into account the size of the capacitive load being driven. digital i/o port the ad5744r contains a 2-bit digital i/o port (d1 and d0). these bits can be configured independently as inputs or outputs and can be driven or have their values read back via the serial interface. the i/o port signals are referenced to dv cc and dgnd. when configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system. when configured as inputs, the logic signals from limit switches, for example, can be applied to d0 and d1 and can be read back using the digital interface. die temperature sensor the on-chip die temperature sensor provides a voltage output that is linearly proportional to the celsius temperature scale. its nom- inal output voltage is 1.47 v at 25c die temperature, varying at 5 mv/c, giving a typical output range of 1.175 v to 1.9 v over the full temperature range. its low output impedance and linear output simplify interfacing to temperature control circuitry and analog-to- digital converters (adcs). the temperature sensor is provided as more of a convenience than as a precise feature; it is intended for indicating a die temperature change for recalibration purposes. local ground offset adjust the ad5744r incorporates a local ground offset adjust feature that, when enabled in the function register, adjusts the dac outputs for voltage differences between the individual dac ground pins and the refgnd pin, ensuring that the dac output voltages are always referenced to the local dac ground pin. for example, if the agnda pin is at +5 mv with respect to the refgnd pin, and vouta is measured with respect to agnda, a ?5 mv error results, enabling the local ground offset adjust feature to adjust vouta by +5 mv, thereby eliminating the error.
ad5744r rev. a | page 27 of 32 applications information typical operating circuit figure 43 shows the typical operating circuit for the ad5744r. the only external components needed for this precision 14-bit dac are decoupling capacitors on the supply pins and reference inputs and an optional short-circuit current setting resistor. because the ad5744r incorporates a voltage reference and reference buffers, it eliminates the need for an external bipolar reference and associated buffers, resulting in an overall savings in both cost and board space. in figure 43 , av dd is connected to +15 v, and av ss is connected to ?15 v; but av dd and av ss can operate with supplies from 11.4 v to 16.5 v. in figure 43 , agndx is connected to refgnd. precision voltage reference selection to achieve the optimum performance from the ad5744r over its full operating temperature range, an external voltage reference must be used. care must be taken in the selection of a precision voltage reference. the ad5744r has two reference inputs, refab and refcd. the voltages applied to the reference inputs are used to provide a buffered positive and negative reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the device. there are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise. initial accuracy error on the output voltage of an external refer- ence could lead to a full-scale error in the dac. therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr425 , allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. the trim adjustment can also be used at temperature to trim out any error. long term drift is a measure of how much the reference output voltage drifts over time. a reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of a reference output voltage affects inl, dnl, and tue. a reference with a tight temperature coef- ficient specification should be chosen to reduce the dependence of the dac output voltage on ambient conditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. it is important to choose a reference with as low an output noise voltage as practical for the system resolution that is required. precision voltage references, such as the adr435 (xfet? design), produce low output noise in the 0.1 hz to 10 hz region. however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. table 18. some precision references recommended for use with the ad5744r part no. initial accuracy (mv maximum) long-term drift (ppm typical) temperature drift (ppm/c maximum) 0.1 hz to 10 hz noise (v p-p typical) adr435 6 30 3 3.5 adr425 6 50 3 3.4 adr02 5 50 3 10 adr395 6 50 25 5 ad586 2.5 15 10 4
ad5744r rev. a | page 28 of 32 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad5744r sync sclk sdin sdo d0 ldac clr d1 vouta voutb agndb voutd voutc agndc agnda agndd rstout rstin dgnd dv cc av dd pgnd av ss iscc bin/2scomp av dd av ss temp refgnd refout refcd refab sync sclk sdin sdo ldac d0 d1 rstout rstin bin/2scomp +5v +5v +15v ?15v +15 v ? 15 v vouta voutb voutc voutd 100nf 100nf 100nf 10f 100nf 100nf 10f 10f 10f temp 10f 10f 06065-064 figure 43. typical operating circuit
ad5744r rev. a | page 29 of 32 layout guidelines in any circuit where accuracy is important, careful considera- tion of the power supply and grou nd return layout helps to ensure the rated performance. design the pcb on which the ad5744r is mounted such that the analog and digital sections are separated and confined to certain areas of the board. if the ad5744r is in a system where multiple devices require an agndx-to-dgnd connection, establish the connection at one point only. establish the star ground point as close as possible to the device. the ad5744r should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up agains t the device. the 10 f capaci- tors are of the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5744r should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. shield fast- switching signals, such as cloc ks with digital ground to avoid radiating noise to other parts of the board; they should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce cross-talk between them. (a ground line is not required on a multi-layer board because it has a separate ground plane; howe ver, it is helpful to separate the lines.) it is essential to minimize noise on the reference inputs because it couples through to the dac output. avoid crossover of digital and analog signals. run traces on opposite sides of the board at right angles to each other to reduce the effects of feed- through on the board. a micros trip technique is recommended but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane, and the signal traces are placed on the solder side. galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. isocou- plers provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5744r makes it ideal for isolated interfaces because the number of interface lines is kept to a min- imum. figure 44 shows a 4-channel isolated interface to the ad5744r using an adum1400 i coupler? product. for more information on i coupler products, refer to www.analog.com . microprocessor interfacing microprocessor interfacing to the ad5744r is accomplished using a serial bus that uses standard protocol that is compatible with microcontrollers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. the ad5744r requires a 24-bit data-word with data valid on the falling edge of sclk. for all the interfaces, a dac output update can be performed automatically when all the data is clocked in, or it can be done under the control of ldac . the contents of the dac register can be read using th e readback function. v ia serial clock out to sclk v oa encode decode v ib serial data out to sdin v ob encode decode v ic sync out to sync v oc encode decode v id control out to ldac v od encode decode microcontroller adum1400* *additional pins omitted for clarity. 06065-065 figure 44. isolated interface
ad5744r rev. a | page 30 of 32 outline dimensions compliant to jedec standards ms-026-ab a 0.45 0.37 0.30 0.80 bsc lead pitch 7.00 bsc sq 9.00 bsc sq 1 24 25 32 8 9 17 16 1.20 max 0.75 0.60 0.45 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity seating plane 0 min 7 3.5 0 0.15 0.05 view a rotated 90 ccw view a pin 1 top view (pins down) 020607-a figure 45. 32-lead thin plastic quad flat package [tqfp] (su-32-2) dimensions shown in millimeters ordering guide model function inl temperature range internal reference package description package option ad5744rcsuz 1 quad 14-bit dac 1 lsb maximum ?40c to +85c +5 v 32-lead tqfp su-32-2 ad5744rcsuz-reel7 1 quad 14-bit dac 1 lsb maximum ?40c to +85c +5 v 32-lead tqfp su-32-2 1 z = rohs compliant part.
ad5744r rev. a | page 31 of 32 notes
ad5744r rev. a | page 32 of 32 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06065-0-12/08(a)

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